In the art of frequency synthesis, there arises a need for a frequency divider which can divide by an arbitrary number, chosen and programmed into the divider by the user. This need is due to the prevalence of phase locked loops in the synthesis art. In these loops, the output signal of a voltage-controlled oscillator (VCO) is divided by such a programmable divider. The divider's output pulse train is then compared with a reference frequency signal and the phase difference of the two is converted into a control signal which is then applied to the VCO. Using negative feedback and proper design of the loop parameters, this will result in stabilizing the value of the phase difference and locking (that is, holding constant) the VCO frequency. If the divider can be programmed to divide by an arbitrary integer N, the VCO will thus be locked to N times the reference frequency. Hence, varying the value of N will make available a range of synthesized signals from the VCO.
To build frequency dividers, it is common in the art to rely on programmable counter integrated circuits (ICs). These are available in both binary and decimal formats and with many different feature combinations. For many applications, a divider may readily be constructed by using programmable counters, either singly or in combination. A typical divider is composed of cascaded (i.e., chained together) counter ICs in sufficient number to accomodate the largest value of N required. Each IC is responsible for one digit (decimal counter) or 4 or more bits (binary counter). FIG. 1 shows an example of how to construct a frequency divider for dividing a signal frequency of 20 MHz by a decimal integer from 2 to 1000. Three binary-coded-decimal (BCD) programmable counter ICs 10, 11, 12 are connected in cascade. The signal to be divided is supplied in the form of a logic clock 13 coupled to the clock inputs 14. Each counter has a count enable input (CE) which must be high (asserted) to enable counting, a terminal count (TC) output which becomes high when the internal count reaches nine, and a program enable input (PE) for enabling a BCD number to be loaded into its internal registers. Because these counters count up, the complement of N (1000-N) is made available and is partitioned into units, tens, and hundreds components which are supplied to the program inputs 21, 22, and 23, respectively. CE 25 is always enabled, so the units counter 10 counts continually. Each time its contents reach nine, TC output 16 becomes high for one clock cycle, falling to zero as the counter's contents transition from nine to zero. The coupling from TC 16 to CE 19 enables the tens counter 11 to advance one count on the next clock cycle. Similiar control is exercised by counter 11 on the hundreds counter 12 by connecting TC 17 to CE 20. When the maximum count value 999 is reached, TC 18 becomes high and, by asserting all PE inputs 15, causes each counter to reload the digit at its programming input and thus the divider begins a new cycle. TC 18 also is the source of the divider output signal 24.
A typical choice for the counter IC is the 74LS162, a TTL part specified to have a count rate of at least 25 MHz.
It would surprise some builders of this divider, however, to discover that its maximum speed is much less than 25 MHz. This reduced performance is caused by the additional times required by the interconnections among the counters. The critical event for the divider is the transition after the maximum count is reached. In addition to the clock-TC delay (35 nS), the circuit must accomodate two CE setup times (40 nS) and a PE setup (20 nS), for a total of 95 nS. This corresponds to a maximum frequency for the divider of 1/(95 nS) or 10.5 Mhz:
One way to realize a higher speed programmable divider is to choose a faster logic family, such as ECL. This will increase the speed by a factor of 5 or more over the TTL version, but there are several penalties: higher cost, greater power consumption, logic level translation to other circuits, and another power supply. In addition, the maximum frequency of a cascaded ECL divider is lower than that of its individual counters, and for the same reason: additional times required by the interconnections.
Another way to build programmable dividers to operate at higher speeds is to use a dual-modulus counter. This device is a high speed counter whose modulus can be switched between two numbers, such 10 and 11, by a single control line. It has a disadvantage of requiring an additional control counter to determine when to switch the modulus. It has a more serious disadvantage in that there are certain values of N which cannot be used. An illuminating discussion of dual modulus dividers is found in "Digital phase locked loops: theory and design" by Ulrich L. Rohde, Prentice-Hall 1983, pages 276ff.
For those requiring a programmable divider to operate near the high frequency end of the art, currently approaching a gigahertz, the options are few. Accordingly, there is a need for achieving higher frequency performance from divider circuits composed of commercially available counter ICs.